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SEMICONDUCTOR POWER TECHNOLOGIES INC
MANHATTAN, KS, 66502
UnclaimedClaim this profile (free)
Subcontracting experience
1 record from government sources. Past participation is not evidence of current teaming interest.
| Role | Agency | Description | Vehicle | Obligated | Action date | Period |
|---|---|---|---|---|---|---|
| Subcontractor | Department of Defense | "TASK 1: CUSTOM DSRD EPITAXY DOPANT PROFILE. SEPTEMBER 1, 2024 €€Œ MARCH 1, 2025
THIS TASK IS FOR A CUSTOM SI EPITAXY (EPI) DOPANT PROFILE GROWN ON 200MM SI WAFERS. THE DOPANT
PROFILE WILL BE DETERMINED BY MODELING BY UMKC TEAM. THE EPI PROFILE WILL BE MANUFACTURED BY
LAWRENCE SEMICONDUCTOR RESEARCH LAB (LSRL).
A. 25 WAFERS, 200MM DIA., WILL BE MANUFACTURED TO ALLOW FOR WAFER BREAKAGE DURING THE EDGE
PASSIVATION GROOVE FABRICATION, WAFER THINNING PROCESS IN TASK 3 AND KNOWN PARTICLES FROM EPITAXY
PROCESS REDUCING TOTAL CHIP YIELD.
TASK 2: INCREASED DSRD STATIC BREAKDOWN VOLTAGE. MARCH 1, 2025 €€Œ MAY 1, 2025 FABRICATION OF
V-GROOVES IN EPITAXY LAYER AND OXIDATION (OR OTHER DIELECTRIC) PASSIVATION OF THE DEVICE EDGE.
A. WILL PURCHASE AND USE BLANK TEST WAFERS FOR FIRST TEST ARTICLES BEFORE USING EPI-WAFERS;
B. CHIP AREA WILL BE DETERMINED IN TASK 3;
C. V-GROOVES WILL BE ETCHED WITH WET ETCHANT TO FORM PYRAMIDAL CHIPS;
D. DIODE EDGE WILL BE PASSIVATED WITH A THERMAL OXIDE (OR OTHER DIELECTRIC) TO INCREASE
BREAKDOWN VOLTAGE OF INDIVIDUAL CHIPS.
SEMICONDUCTOR POWER TECHNOLOGIES, INC. (SPT)
4780 LAKE ELBO ROAD, KS 66502
WWW.SEMIPT.COM
INNOVATION IN PULSED POWER
TASK 3: DSRD WAFER/CHIP THINNING AND CHIP AREA. MAY 1, 2025 €€Œ JULY 31, 2025
WAFERS WILL BE BACKSIDE THINNED AFTER GROOVES TO THE THICKNESS OF THE EPITAXY LAYER STACKUP.
BACKSIDE OF WAFER WILL BE METALIZED WITH A METAL STACK UP REQUIRED FOR METAL BONDING BETWEEN CHIPS
AND/OR HEATSINKS.
A. WILL PURCHASE AND USE BLANK TEST WAFERS FOR FIRST TEST ARTICLES BEFORE USING EPI-WAFERS;
B. CHIP AREA WILL BE DETERMINED BY UMKC GROUP;
A. PROPOSED AREA 2 CM² AND 4 CM²;
C. BACKSIDE METAL WILL BE DEPOSITED VIA EVAPORATION METHODS, ELECTROLESS DEPOSITION METHODS, AND/OR
JET-DEPOSITION.
TASK 4: DSRD CHIP STACKING AND PACKAGING. AUG. 1, 2025 €€Œ DEC. 31, 2025
THIS TASK IS FOR A CUSTOM DSRD CHIP STACK ASSEMBLY AND PACKAGING TO MEET THE 100KV DC HOLDOFF
VOLTAGE.
PLAN FOR 20 TOTAL WAFERS TO SURVIVE AND 25-50 CHIPS PER WAFER TO MEET DC SPECIFICATIONS DEPENDING
ON REQUIRED CHIP SIZE.
QTY. 5 OF DSRD CHIP STACKING INCLUDES:
A. HIGH VOLTAGE INSULATION AS NEEDED TO ENSURE PROTOTYPE MEETS DESIGN SPECIFICATIONS AS PER
INTENDED;
B. POSSIBLE HEAT SINKS BETWEEN CHIPS, DEPENDING ON INDUCTANCE REQUIREMENTS;
C. OUTPUT END CONNECTORS RATED AND QUANTITY. FINAL CONNECTOR CHOICES WILL BE COORDINATED BETWEEN
ALEX USENKO AND STEVEN BELLINGER;
D. PROOF OF OPERATION TESTING AT 100KV.
BASE PERIOD OF PERFORMANCE BUDGET:
TASK 1: CUSTOM DSRD EPITAXY DOPANT PROFILE $70,000
TASK 2: INCREASED DSRD STATIC BREAKDOWN VOLTAGE $20,000
TASK 3: DSRD WAFER/CHIP THINNING AND CHIP AREA $35,000
TASK 4: DSRD CHIP STACKING AND PACKAGING $25,000
TOTAL $150,000
ESTIMATED TARGET DELIVERY DATE: OCT. 1, 2025, BUT WIDELY DEPENDENT ON COMPONENT LEAD TIMES.
OPERATIONAL PROTOTYPE DELIVERY THRESHOLD DATE: DEC. 31, 2025." 135632 Parent award context Parent award agency: Department of Defense · Department of the Navy Parent award NAICS: 541715 Parent award performance state: MO Parent award description: PULSED TACTICAL EFFECTOR FOR REGULATED ATTACK (PTERA) View parent award on USAspending | — | $150,000 | Oct 21, 2024 | — – — |
Contract vehicles are shown only when present in the source record. Linked award numbers and vehicles open the authoritative record on USAspending.gov.
Government-sourced data comes from SAM.gov, SBA and USAspending.gov and is attributed to its source. Items marked company-reported were provided by the company and are verified by FedSub only where labeled. FedSub is a private company and is not affiliated with SBA, GSA/SAM.gov, or any government agency.